1. Field of the Invention
The invention relates to a memory circuit integrated on a semiconductor chip. A preferred but not exclusive area of application for the invention is “DRAMs”, i.e., dynamic random access memories.
2. Description of the Related Art
A memory chip accommodates a large multiplicity of memory cells in one or more separate “banks” which respectively occupy a cohesive region of the chip surface. Each bank contains the memory cells typically in a matrix-like arrangement of rows and columns, a switching network which covers the matrix and comprises row and column selection lines (“word lines” and “bit lines”), and also address decoders, line switches, drivers and data amplifiers, in order to connect selected memory cells to data connections on the bank on the basis of address bits, so that data can be written to or read from these cells. In addition, each bank has connections for control signals in order to control the read and write modes. These control signals include not only the address bits but also various time control and switching signals for controlling the flow of the read and write cycles.
The supply voltage is applied, external control signals (clock signals, address bits and control commands) are input and data signals are input and output on the memory chip via external supply lines which are directly and electrically connected to associated contact areas or the “connection pads” on the chip. Between these pads and the internal signal lines connected to the memory bank connections are various circuit arrangements which ensure that the external control signals are transferred to the associated bank control lines in a prescribed logic combination and synchronization and that the data signals are transferred in a prescribed association between the banks' data lines and the data connection pads, respectively. These circuit arrangements thus basically form an “interface system” between the connection pads and the memory bank connections or the internal signal lines routed to these connections. The connection pads, the “interface system” and also the internal signal lines are integrated in regions of the chip surface which are situated outside the surface region occupied by the memory banks.
The market for memory circuits which are mass produced as integrated chips on semiconductor chips is subject to great fluctuations. This applies not only to the demand for memory chips per se but also, in particular, to the rapidly changing demand for different specifications for such chips.
Chip producers want to be able to react as quickly as possible to any demand. However, this is obstructed by the fact that the fabrication time for memory chips is relatively long (e.g., it is currently between four and six months). For this reason, it has become widespread customary practice to design memory chips such that they can be set to one of a plurality of alternative specifications at a stage as late as possible in the production process or even not until the chips are being used in practice. The latter option, i.e., setting during use, is appropriate only for a few operating parameters, e.g., for the burst length (length of the data sequence which is written or read during each access operation) or the “CAS latency” (waiting time between the activation command and the start of the actual read or write mode). In this context, the parameters are set by setting particular bits in a mode register integrated on the chip on the basis of a command from the external memory controller, i.e., more or less by software in the course of operational control.
However, there are also operating or specification parameters whose market-dependent range of fluctuation should be taken into account by virtue of appropriate design of the chip hardware, specifically by virtue of the circuit design of the aforementioned interface system. Such parameters include, by way of example, the data rate relative to the storage clock, the frequency of the storage clock, the frequency of the system clock, the bit length of the data stream sent and received, the external supply voltage and the voltage values of the logic levels in the data sent and received.
To be able to allow for different alternative modes of operation, it is known practice to design integrated memory chips as “combo” chips. In this context, as many elements of the interface system as possible are designed such that they can work in any of the alternative modes of operation, i.e., work “universally”. If the various modes of operation require different patterns of signal paths between the existing universal elements, the connection pads and the internal signal lines, then a complex system of logic gates is additionally provided which is capable of producing each of the different signal path patterns on the basis of control potentials. The connections between the logic system and the respective control potential sources are set up prior to delivery of the chip by means of a contact-making operation in the topmost metallization plane. Since this can take place at a very late production stage, e.g., directly before the chip is encapsulated, alignment with the market can be carried out at short notice.
Such customary combo chips have their own drawbacks, however. Since many elements of the interface system and also of the logic system need to work in different modes of operation, compromises are needed in terms of the design and the dimensioning of these elements. Many elements which may have optimum properties for one particular mode of operation will work less well for another mode of operation. Thus, there is little success in designing the interface system in optimum fashion for all modes of operation.